Visible to Intel only — GUID: sfo1411572546903
Ixiasoft
Visible to Intel only — GUID: sfo1411572546903
Ixiasoft
7.2.2. Arm* JTAG-AP Scan Chains
Scan chain 7 of the JTAG-AP connects to FPGA JTAG TAP controller. When the system manager undergoes a cold reset, this connection is disabled and the FPGA JTAG pins are connected to the FPGA JTAG TAP controller. You can configure the system manager to enable the connection, which allows software running on the HPS to communicate with the FPGA JTAG TAP controller. In this case, software can send JTAG commands (such as the SHIFT_EDERROR_REG JTAG instruction) to the FPGA JTAG and get responses to determine details about CRC errors detected by the control block when the FPGA fabric is in user mode. Through the FPGA manager, software can determine that a CRC error was detected. For more information about the TAP controller, refer to the Communicating with the JTAG TAP Controller section of this chapter.
Scan chains 0 to 3 of the JTAG-AP connect to the configuration information in the HPS I/O scan chain banks through the I/O configuration shift register (IOCSR) multiplexer. For more information, refer to the Configuring HPS I/O Scan Chains section of this chapter.
The HPS I/O pins are divided into six banks. Each I/O bank is either a vertical (VIO) or horizontal (HIO) I/O, based on its location on the die.
IOCSR Scan Chain |
Bank Type |
HPS I/O Bank |
Usage |
---|---|---|---|
0 |
VIO |
I/O bank 7D and I/O bank 7E |
EMAC |
1 |
VIO |
I/O bank 7B and I/O bank 7C |
SD/MMC, NAND, and quad SPI |
2 |
VIO |
I/O bank 7A |
Trace, SPI, UART, and I2C |
3 |
HIO |
I/O bank 6 |
SDRAM DDR |
When the FPGA JTAG TAP controller is in CONFIG_IO mode, the controller can override the scan manager JTAG-AP and configure the HPS I/O pins. For more information, refer to the Configuring HPS I/O Scan Chains section of this chapter.
- DDR SDRAM
- OSC1/2
- Warm/Cold reset