Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

A.3. Booting and Configuration Options

SoC initialization includes the booting of the HPS and the configuration of the FPGA fabric and I/O.

Depending on the initialization option you choose, the I/O configuration is handled differently. You can choose one of the three initialization options:

  • The HPS boot and FPGA configuration occur separately.
  • The HPS boots first and then configures the FPGA.
  • The HPS boots from the FPGA after the FPGA is configured.
Note: The HPS and FPGA portions of the device have separate external power supplies and independently power on. You can power on the HPS without powering on the FPGA portion of the device. However, to power on the FPGA portion, the HPS must already be on or powered at the same time as the FPGA portion. You can also turn off the FPGA portion of the device while leaving the HPS power on.

The following three figures illustrate the possible HPS boot and FPGA configuration schemes. The arrows in the figures denote the data flow direction.

Figure 140. Separate FPGA Configuration and HPS Booting

In the figure below, the FPGA configuration and HPS boot can occur independently. The FPGA obtains its configuration image from a non-HPS source, while the HPS boot ROM obtains its preloader from a non-FPGA fabric source.

Figure 141. HPS Boots First and then Configures the FPGA

In the figure below, the HPS boots first through one of its non-FPGA fabric boot sources. The FPGA does not need to be configured in order for the HPS to boot. However, the FPGA must be in a power-on state for the HPS to reset properly. The software on the HPS obtains the FPGA configuration image from any of its flash memory devices or communication interfaces, for example, the Ethernet media access controller (EMAC).

Figure 142. HPS Boots From FPGA

In the figure below, the FPGA is configured first through one of its non-HPS configuration sources and then the HPS executes the preloader from the FPGA. In this situation, the HPS should not be released from reset until the FPGA is powered on and programmed. Once the FPGA is in user mode and the HPS has been released from reset, the boot ROM code begins executing. The HPS boot ROM code executes the preloader from the FPGA fabric over the HPS-to-FPGA bridge.