Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

16.2. Quad SPI Flash Controller Block Diagram and System Integration

Figure 67. Quad SPI Flash Controller Block Diagram and System Integration

The quad SPI controller consists of the following blocks and interfaces:

  • Register slave interface—Slave interface that provides access to the control and status registers (CSRs)
  • Data slave controller—Slave interface and controller that provides the following functionality:
    • Performs data transfers to and from the level 3 (L3) interconnect
    • Validates incoming accesses
    • Performs byte or half-word reordering
    • Performs write protection
    • Forwards transfer requests to direct and indirect controller
  • Direct access controller—provides memory-mapped slaves direct access to the flash memory
  • Indirect access controller—provides higher-performance access to the flash memory through local buffering and software transfer requests
  • Software triggered instruction generator (STIG)—generates flash commands through the flash command register (flashcmd) and provides low-level access to flash memory
  • Flash command generator—generates flash command and address instructions based on instructions from the direct and indirect access controllers or the STIG
  • DMA peripheral request controller—issues requests to the DMA peripheral request interface to communicate with the external DMA controller
  • SPI PHY—serially transfers data and commands to the external SPI flash devices