Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

20.4.2.1.2. SPI Slave Bit-Rate Clock

The minimum frequency of l4_main_clk depends on the operation of the slave peripheral. If the slave device is receive only, the minimum frequency of l4_main_clk is six times the maximum expected frequency of the bit‑rate clock from the master device (sclk_in). The sclk_in signal is double synchronized to the l4_main_clk domain, and then it is edge detected; this synchronization requires three l4_main_clk periods. †

If the slave device is transmit and receive, the minimum frequency of l4_main_clk is eight times the maximum expected frequency of the bit‑rate clock from the master device (sclk_in). This ensures that data on the master rxd line is stable before the master shift control logic captures the data.  †

The frequency ratio restrictions between the bit‑rate clock sclk_in and the SPI slave peripheral clock are as follows: †

  • Slave (receive only): Fl4_main_clk >= 6 multiply (maximum Fsclk_in) †
  • Slave: Fl4_main_clk >= 8 multiply (maximum Fsclk_in) †