Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

14.4.1. Discovery and Initialization

The NAND flash controller performs a specific initialization sequence after the HPS receives power and the flash device is stable. During initialization, the flash controller queries the flash device and configures itself according to one of the following flash device types:
  • ONFI 1.0-compliant devices
  • Legacy (non‑ONFI) NAND devices

The NAND flash controller identifies ONFI‑compliant connected devices using ONFI discovery protocol, by sending the Read ID command. For devices that do not recognize this command (especially for 512‑byte page size devices), software must write to the system manager to assert the bootstrap_512B_device signal to identify the device type before releasing the NAND controller from reset.

To support booting and initialization, the rdy_busy_in pin must be connected.

The NAND flash controller performs the following initialization steps:

  1. If the system manager is asserting bootstrap_inhibit_init, the flash controller goes directly to step 7.
  2. When the device is ready, the flash controller sends the "Read ID" command to read the ONFI signature from the memory device, to determine whether an ONFI or a legacy device is connected.
  3. If the data returned by the memory device has an ONFI signature, the flash controller then reads the device parameter page. The flash controller stores the relevant device feature information in internal memory control registers, enabling it to correctly program other registers in the flash device, and goes to step 5.
  4. If the data does not have a valid ONFI signature, the flash controller assumes that it is a legacy (non‑ONFI) device. The flash controller then performs the following steps:
    1. Sends the reset command to the device
    2. Reads the device signature information
    3. Stores the relevant values into internal memory controller registers
  5. The flash controller resets the memory device. At the same time, it verifies the width of the memory interface. The HPS supports one 8‑bit NAND flash device. As a result, the flash controller always detects an 8-bit memory interface.
  6. The flash controller sends the Page Load command to block 0, page 0 of the device, configuring direct read access, so the processor can boot from that page. The processor can start reading from the first page of the flash memory, which is the expected location of the pre-loader software.
    Note: The system manager can bypass this step by asserting bootstrap_inhibit_b0p0_load before reset is de-asserted.
  7. The flash controller sends the reset command to the flash.
  8. The flash controller clears the rst_comp bit in the intr_status0 register in the status group to indicate to software that the flash reset is complete.