Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

20.4.1. Protocol Details and Standards Compliance

This section describes the functional operation of the SPI controller. 

The host processor accesses data, control, and status information about the SPI controller through the system bus interface. The SPI also interfaces with the DMA Controller. †

The HPS includes two general‑purpose SPI master controllers and two general‑purpose SPI slave controllers.

The SPI controller can connect to any other SPI device using any of the following protocols:

  • Motorola SPI Protocol †
  • Texas Instruments Serial Protocol (SSP) †
  • National Semiconductor Microwire Protocol †