Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

14.4.9.2. Burst DMA Command

You can initiate a DMA transfer by sending a command to the NAND flash controller as a burst transaction of four 16‑bit accesses. This form of DMA command might be useful for initiating DMA transfers from custom IP in the FPGA fabric. Most processor cores cannot use this form of DMA command, because they cannot control the width of the burst.

When DMA is enabled, the NAND flash controller recognizes the MAP10 pipeline DMA command as an INCR4 command, in the format shown in the following table. The address decoding for MAP10 pipeline DMA command remains the same, as shown in "MAP10 Command Format".

MAP10 commands in INCR4 format are written to the Data register at offset 0x10 in nanddata, the same as MAP10 commands in multitransaction format (described in the "Multi-Transaction DMA Command").

Table 119.  MAP10 Burst DMA (INCR4) Command StructureThe following table lists the MAP10 burst DMA command structure. The burst DMA command carries the same information as the multi-transaction DMA command‑data pairs, but in a very different format.
Data Beat 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Beat 0 0x2 0x0: read. 0x1: write. <PP>=number of pages
Beat 135 Memory address high
Beat 235 Memory address low
Beat 3 0x0 INT36 Burst length
Note: INT controls the value of the dma_cmd_comp bit of the intr_status0 register in the status group at the end of the DMA transfer. INT can take on one of the following values:

0—Do not interrupt host. The dma_cmd_comp bit is set to 0.

1—Interrupt host. The dma_cmd_comp p bit is set to 1.

You can optionally send the 16‑bit fields in the above table to the NAND flash controller as four separate bursts of length 1 in sequential order. Intel recommends this method.

If you want the NAND flash controller DMA to perform cacheable accesses, you must configure the cache bits by writing the l3master register in the nandgrp group in the system manager. The NAND flash controller DMA must be idle before you use the system manager to modify its cache capabilities.

35 The buffer address in host memory, which must be aligned to 32 bits.
36 INT specifies the host interrupt to be generated at the end of the complete DMA transfer. For more information about INT, see the Note at the bottom of this table.