Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

3.3.3.1. OSC1 Clock Group

The clock in the OSC1 clock group is derived directly from the HPS_CLK1 pin. This clock is never gated or divided.

HPS_clk1 is used as a PLL input and also by HPS logic that does not operate on a clock output from a PLL.

Table 8.  OSC1 Clock Group Clock

Name

Frequency

Clock Source

Destination

osc1_clk

0 to 100 MHz

HPS_CLK1 pin

OSC1-driven peripherals. Refer to "Main Clock Group Clocks".