Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

20.4.4. SPI Master

The SPI master initiates and controls all serial transfers with serial‑slave peripheral devices. †

The serial bit‑rate clock, generated and controlled by the SPI controller, is driven out on the sclk_out line. When the SPI controller is disabled, no serial transfers can occur and sclk_out is held in “inactive” state, as defined by the serial protocol under which it operates. †