Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

12.8.1. DDR Calibration

The SDRAM Controller calibrates across multiple SDRAM banks. An entire row is calibrated at bank 0 and bank 7 in each rank. Thus, if you have a 4 Gb memory made up of two ranks, rank 0 is calibrated in banks 0 and 7, and rank 1 is calibrated in banks 0 and 7.

You can refer to the "Interleaving Options" section to identify which memory locations are affected by calibration.
Note: The SDRAM Controller does not preserve memory contents through a calibration cycle.