MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs

ID 817561
Date 4/01/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.2.1.85. TX_TM_CONTROL

Offset: 0x70
Default: 0x00
Description: TX test mode control register
Bit Name Access Description
2 TX_TM_CONTROL_TX_TST_CNT_RST RWSC TX count reset - write 1 to clear all TX counters - (future enhancement).
1 TX_TM_CONTROL_TX_TM_LOOPBACK_MODE Read Write TX HS_TEST loopback mode - (future enhancement).
0 TX_TM_CONTROL_TX_TM_EN Read Write TX HS_TEST mode enable - (future enhancement).