MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs

ID 817561
Date 4/01/2024
Public

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Document Table of Contents

6.2.1.67. RX_HS_SETTLE

Offset: 0x52
Default: IP Param
Description: RX_HS_SETTLE
Bit Name Access Description
7:0 RX_HS_SETTLE Read Write *

RX _HS_SETTLE

Time interval during which the HS receiver shall ignore any Data Lane HS transitions, starting from the beginning of THS-PREPARE. The HS receiver shall ignore any Data Lane transitions before the minimum value, and the HS receiver shall respond to any Data Lane transitions after the minimum val

Delay computation (approx):

THS-SETTLE = (RX_HS_SETTLE + 7) * Core_CLK_period + RX_CLK_period
Note: * Can be configured as Read Only during IP generation to save resources.