MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs

ID 817561
Date 4/01/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.2.1.43. RX_DLANE_DESKEW_DELAY_5

Offset: 0x36
Default: IP Param
Description: RX Data lane deskew delay 5
Bit Name Access Description
6:0 RX_DLANE_DESKEW_DELAY_5 Read Write *

RX Data lane deskew delay 5.

Manual data Lane 5 deskew delay setting.
Note: * Can be configured as Read only during IP generation to save resources.