MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs

ID 817561
Date 4/01/2024
Public

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6.2.1.76. RX_DESKEW_DELAY_MUX

Offset: 0x66
Default: 0x00
Description: RX deskew delay for lane CAL_REG_MUXSEL
Bit Name Access Description
6:0 RX_DESKEW_DELAY_MUX Read Only

RX deskew delay for lane CAL_REG_MUXSEL

- this register is updated during calibration or manual deskew writes

- default value is 0 and might not reflect the actual deskew for lane until calibration or manual deskew writes.