MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs

ID 817561
Date 4/01/2024
Public

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Document Table of Contents

6.2.1.70. RX_CAL_REG_CTRL

Offset: 0x60
Default: IP Param
Description: RX Capability Register
Bit Name Access Description
3 RX_CAL_REG_CTRL_CAL_RESET RWSC Recalibrate (next skew will be treated as init skew cal) - self clearing for all lanes.
2:0 RX_CAL_REG_CTRL_CAL_REG_MUXSEL Read Write Cal/debug reg mux select (0 - 7 for 8 data lanes) index.