MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs

ID 817561
Date 4/01/2024
Public

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6.2.1.36. RX_DLANE_ERR_3

Offset: 0x2F
Default: 0x00
Description: Data Lane 3 error status register (RX)
Bit Name Access Description
6 RX_DLANE_ERR_3_CAL_ERR RW1C Calibration error.
5 RX_DLANE_ERR_3_CTRL_ERR RW1C False control error.
4 RX_DLANE_ERR_3_LPDT_ERR RW1C LP transmission sync error.
3 RX_DLANE_ERR_3_ESC_ENTRY_ERR RW1C ESC mode entry error.
2 RX_DLANE_ERR_3_EOT_SYNC_ERR RW1C EoT sync error.
1 RX_DLANE_ERR_3_SOT_SYNC_ERR RW1C SoT sync error.
0 RX_DLANE_ERR_3_SOT_ERR RW1C SoT error