MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs

ID 817561
Date 4/01/2024
Public

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Document Table of Contents

6.2.1.50. DLANE_STATUS_7

Offset: 0x3D
Default: 0x00
Description:  
Bit Name Access Description
0 DLANE_STATUS_7_INIT_DONE Read Only

Data lane init done.

For TX with SKEW_CAL_EN (and ALT_CAL_EN) set to 1, this only gets asserted after the calibration is done.