MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs

ID 817561
Date 4/01/2024
Public

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Document Table of Contents

6.2.1.60. TX_HS_PREPARE

Offset: 0x49
Default: IP Param
Description: TX_HS_PREPARE
Bit Name Access Description
5:0 TX_HS_PREPARE Read Write *

TX _HS_PREPARE

Time that the transmitter drives the Data Lane LP-00 Line state immediately before the HS-0 Line state starting the HS transmission.

Delay computation (approx):

THS-PREPARE = (TX_HS_PREPARE + 2) * Core_CLK_period.
Note: * Can be configured as Read Only during IP generation to save resources.