MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs

ID 817561
Date 4/01/2024
Public

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4.5. I/O Bank Sharing

You can use the remaining unused I/O lanes in the I/O bank for MIPI with other implementations using the same I/O voltage.

The MIPI D-PHY IP currently supports 1.1 V or 1.2 V implementation.

The MIPI D-PHY pin uses the D-PHY I/O standard in the Quartus® Prime software. The Quartus® Prime software defaults the VCCIO_PIO of the sub-bank to 1.2 V when the D-PHY I/O standard is used.

Follow these steps if you intend to use D-PHY at 1.1 V VCCIO_PIO:

  1. Assign the MIPI D-PHY reference clock and RZQ pin to 1.1 V with a QSF assignment or in the Pin Planner. The reference clock can be LVCOMS or true differential signaling, depending on the selection on the MIPI D-PHY IP.
  2. Use the following QSF assignment to assign the VCCIO_PIO of the sub-bank to 1.1 V. You must set the assignment for both top and bottom sub-bank if your MIPI D-PHY design is placed on both the top and bottom sub-banks:
    set_global_assignment -name IOBANK_VCCIO 1.1V -section_id <sub_bank_name>
    For example:
    set_global_assignment -name IOBANK_VCCIO 1.1V -section_id 3B_B