MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs

ID 817561
Date 4/01/2024
Public

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Document Table of Contents

6.2.1.61. TX_HS_ZERO

Offset: 0x4A
Default: IP Param
Description: TX_HS_ZERO
Bit Name Access Description
7:0 TX_HS_ZERO Read Write *

TX _HS_ZERO.

Time that the transmitter drives the HS-0 state prior to transmitting the Sync sequence.

Delay computation (approx): (+ TXFIFO_LAT is intended)

THS-ZERO = (TX_HS_ZERO + 3 + TXFIFO_LAT) * Core_CLK_period + (PPI_16 ? 8UIs : 0).
Note: * Can be configured as Read Only during IP generation to save resources.