MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs

ID 817561
Date 4/01/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.2.1.58. TX_CLK_POST

Offset: 0x47
Default: IP Param
Description: TX_CLK_POST
Bit Name Access Description
7:0 TX_CLK_POST Read Write *

TX_CLK_POST.

Time that the transmitter continues to send HS clock after the last associated Data Lane has transitioned to LP mode. Interval is defined as the period from the end of THS-TRAIL to the beginning of TCLK-TRAIL.

Delay computation (approx) : (+ TXFIFO_LAT is intended)

TCLK-POST = (TX_CLK_POST + 3 + TXFIFO_LAT) * Core_CLK_period
Note: * Can be configured as Read Only during IP generation to save resources.