MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs

ID 817561
Date 4/01/2024
Public

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6.2.1.35. RX_DLANE_DESKEW_DELAY_3

Offset: 0x2E
Default: IP Param
Description: RX Data lane deskew delay 3
Bit Name Access Description
6:0 RX_DLANE_DESKEW_DELAY_3 Read Write *

RX Data lane deskew delay 3.

Manual data Lane 3 deskew delay setting.
Note: * Can be configured as Read Only during IP generation to save resources.