MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs

ID 817561
Date 4/01/2024
Public

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Document Table of Contents

6.2.1.37. DLANE_CSR_4

Offset: 0x30
Default: IP Param
Description: Data Lane 4 CSR 0
Bit Name Access Description
4 DLANE_CSR_4_RX_MNL_DESKEW_EN Read Write Manual deskew delay enable.
3 DLANE_CSR_4_RX_DESKEW_UPDATE RWSC

A write of '1' to this register will trigger deskew delay update.

MNL_DESKEW_EN = 1 - triggers write from RX_DLANE_DESKEW_DELAY_4

MNL_DESKEW_EN = 0 - triggers write from calibration state machine.
0 DLANE_CSR_4_EN read Write Enable - when enabling, set this register bit first before setting D-PHY_CSR.Enable to 1.