MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs

ID 817561
Date 4/01/2024
Public

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Document Table of Contents

6.2.2.19. TG_RX_OVRD_DATA_PAT

Offset: 0x1A8
Default: 0x00
Description:  
Bit Name Access Description
31:24 TG_RX_OVRD_DATA_PAT_DATA_PAT_OVRD Read Write Data pattern override (1 bit per data lane).
23:16 TG_RX_OVRD_DATA_PAT_LP_DATA Read Write LP data pattern to use for checking instead of the generated pattern.
15:0 TG_RX_OVRD_DATA_PAT_HS_DATA Read Write HS data pattern to use for checking instead of the generated pattern. NOTE: checker will not be able to compute THS-SKIP if HS-DATA is all 0's or all 1's.