MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs

ID 817561
Date 4/01/2024
Public

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Document Table of Contents

6.2.1.77. RX_CAL_STATUS_LANE_MUX

Offset: 0x67
Default: 0x00
Description: Calibration status for lane CAL_REG_MUXSEL
Bit Name Access Description
4 RX_CAL_STATUS_LANE_MUX_ALT_CAL_ERR_LANE Read Only Alt cal error .
3 RX_CAL_STATUS_LANE_MUX_PER_SKEW_CAL_ERR_LANE Read Only Periodic skew cal error.
2 RX_CAL_STATUS_LANE_MUX_INIT_SKEW_CAL_ERR_LANE Read Only Init Skew cal error.
1 RX_CAL_STATUS_LANE_MUX_ALT_CAL_DONE_LANE Read Only Alt cal complete.
0 RX_CAL_STATUS_LANE_MUX_SKEW_CAL_DONE_LANE Read Only Skew cal complete.