MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs

ID 817561
Date 4/01/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.2.1.48. RX_DLANE_ERR_6

Offset: 0x3B
Default: 0x00
Description: Data Lane 6 error status register (RX)
Bit Name Access Description
6 RX_DLANE_ERR_6_CAL_ERR RW1C Calibration error.
5 RX_DLANE_ERR_6_CTRL_ERR RW1C False control error.
4 RX_DLANE_ERR_6_LPDT_ERR RW1C LP transmission sync error.
3 RX_DLANE_ERR_6_ESC_ENTRY_ERR RW1C ESC mode entry error.
2 RX_DLANE_ERR_6_EOT_SYNC_ERR RW1C EoT sync error.
1 RX_DLANE_ERR_6_SOT_SYNC_ERR RW1C SoT sync error.
0 RX_DLANE_ERR_6_SOT_ERR RW1C SoT error.