MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs

ID 817561
Date 4/01/2024
Public

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Document Table of Contents

6.2.1.56. TX_CLK_PREPARE

Offset: 0x44
Default: IP Param
Description: TX_CLK_PREPARE
Bit Name Access Description
5:0 TX_CLK_PREPARE Read Write *

TX_CLK_PREPARE

Time that the transmitter drives the Clock Lane LP-00 Line state immediately before the HS-0 Line state starting the HS transmission.

Delay computation (approx):

TCLK-PREPARE = (TX_CLK_PREPARE + 2) * Core_CLK_period.
Note: * Can be configured as Read Only during IP generation to save resources.