MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs

ID 817561
Date 4/01/2024
Public

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6.2.2. D-PHY Traffic Generator (TG) Registers

Table 30.  D-PHY IP Traffic Generator (TG) Register List
Register Offset Width Access Reset Description
TG_TOP_CTRL_0 0x100 8 Read Write 0x00 TG top control register 0 (mirrored) - affects all links.
TG_TOP_CTRL_1 0x101 8 Read Write 0x00 TG top control register 1 (mirrored) - affects all links.
TG_TOP_DONE 0x104 8 Read Only 0x00 Test done, 1 bit per link (mirrored).
TG_TOP_FAIL 0x105 8 Read Only 0x00 Test fail, 1 bit per link (mirrored).
TG_TOP_TEST_EN 0x106 8 Read Only 0x00 Internal test enable (decoded), 1 bit per test (mirrored).
TG_TOP_TEST_LINK 0x107 8 Read Only 0x00 Internal test link decoded, 1 bit per link (mirrored).
TARGET_TEST_CNT 0x108 8 Read Write Param Target test count.
TCHK_CONTROL 0x180 8 Read Write 0x00  
TCHK_LINK_STATUS 0x184 8 Read Only 0x00  
HS_DONE_LANES 0x185 8 Read Only 0x00 HS done per lane (1 bit per lane).
TCHK_LINK_ERR_STATUS 0x188 8 Read Only 0x00  
LANE_ERROR_SOT_LANES 0x189 8 Read Only 0x00 Lane error SOT/SOT SYNC status per lane.
CAL_ERROR_LANES 0x18A 8 Read Only 0x00 Calibration error status per lane.
HS_ERR_LANES 0x18B 8 Read Only 0x00 HS Data transfer error status per lane.
HS_TEST_CNT 0x18C 8 Read Only 0x00 Number of HS test received for lane N where N is controlled by HS_CNT_MUX.
LPDT_TEST_CNT 0x190 8 Read Only 0x00 Number of LPDT test received.
TRIGGER_TEST_CNT 0z194 8 Read Only 0x00 Number of TRIGGER test received.
ULPS_TEST_CNT 0x198 8 Read Only 0x00 Number of ULPS test received.
TG_RX_OVRD_DATA_PAT 0x1A8 8 Read Only 0x00  
TG_RX_BIT_ERROR_CNT 0x1B0 8 Read Only 0x00 Number of bit error found on lane N where N is controlled by HS_CNT_MUX.
TG_RX_HS_TXFER_CNT 0x1B8 8 Read Only 0x00 HS RX total transfer count per lane (from any lane).
TG_LINK_CONTROL 0x1C0 8   0x00  
TG_INIT_CNT 0x1C4 8 Read Write 0x400 Number of ESC clock cycles for TX INIT.
TG_HS_LEN 0x1C8 8 Read Write 0x00  
TG_LP_LEN 0x1CC 8 Read Write 0x00  
TG_SKEW_CAL 0x1D0 8 Read Write 0x20 Initial skew calibration length in UI (rounded down to number of PPI access).
TG_ALT_CAL 0x1D4 8 Read Write 0x40 Alternate skew calibration length in UI (rounded down to number of PPI access)
TG_PER_SKEW_CAL_LEN 0x1D8 8 Read Write 0x04  
TG_TEST_CNT 0x1E0 8 Read Only 0x00 Number of test round completed by TG.
TG_OVRD_DATA_PAT 0x1E8 8 Read Only 0x00  
TG_TX_HS_TXFER_CNT 0x1F8 8 Read Only 0x00 HS TX total transfer count per lane (on any lane).