MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs

ID 817561
Date 4/01/2024
Public

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Document Table of Contents

6.2.1.24. RX_DLANE_ERR_0

Offset: 0x23
Default: 0x00
Description: Data Lane 0 error status register (RX).
Bit Name Access Description
6 RX_DLANE_ERR_0_CAL_ERR RW1C Calibration error.
5 RX_DLANE_ERR_0_CTRL_ERR RW1C False control error.
4 RX_DLANE_ERR_0_LPDT_ERR RW1C LP transmission sync error.
3 RX_DLANE_ERR_0_ESC_ENTRY_ERR RW1C ESC mode entry error.
2 RX_DLANE_ERR_0_EOT_SYNC_ERR RW1C EoT sync error.
1 RX_DLANE_ERR_0_SOT_SYNC_ERR RW1C SoT sync error.
0 RX_DLANE_ERR_0_SOT_ERR RW1C SoT error.