Nios® V Embedded Processor Design Handbook

ID 726952
Date 12/04/2023

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Document Table of Contents Use Reset Request Tab

Table 8.  Use Reset Request Tab Parameter
Use Reset Request Tab Description
Add Reset Request Interface
  • Enable this option to expose local reset ports where a local master can use it to trigger the Nios® V processor to reset without affecting other components in a Nios® V processor system.
  • The reset interface consists of an input resetreq signal and an output ack signal.
  • You can request a reset to the Nios® V processor core by asserting the resetreq signal.
  • The resetreq signal must remain asserted until the processor asserts ack signal. Failure for the signal to remain asserted can cause the processor to be in a non-deterministic state.
  • Assertion of the resetreq signal in debug mode has no effect on the processor's state.
  • The Nios® V processor responds that the reset is successful by asserting the ack signal.
  • After the processor is successfully reset, the assertion of the ack signal can happen multiple times periodically until the de-assertion of the resetreq signal.