Nios® V Embedded Processor Design Handbook

ID 726952
Date 12/04/2023
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8.2.4. Hardware Design Files

The Intel Agilex® 7 FPGA - Custom Instruction Design on Nios® V/g Processor is developed using the Platform Designer. You can generate the hardware files using the build_sof.py Python script.
The example design consists of:
  • Nios® V Processor Intel® FPGA IP
  • On-Chip Memory II Intel® FPGA IP
  • JTAG UART Intel® FPGA IP
  • Processing Engine 1 (PE1) – Declares funct3 as user-defined intermediate (3’bxxx). All custom operations share a single software C-macro. You can select them using funct3 input argument.
  • Processing Engine 2 (PE2) – Defines funct3 as extension index (3’b000 to 3’b111). Each operations have its own C-macros. You can call their respective C-macros.

The processing engine comprises of the following operations, which are selected based on the 3-bits funct3 field.

  • Operation 0: 1’s complement of Data0
  • Operation 1: 2’s complement of Data0
  • Operation 2: Multiply Data0 with Data1
  • Operation 3: Bit reversal of Data0
  • Operation 4: Byte reversal of Data0
  • Operation 5: Word reversal of Data0
  • Operation 6: Lower word merge of Data0 and Data1
  • Operation 7: Higher word merge of Data0 and Data1
Figure 131. Example Design Block Diagram