Nios® V Embedded Processor Design Handbook

ID 726952
Date 12/04/2023
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4.3. Nios® V Processor Booting Methods

There are a few methods to boot up the Nios® V processor in Intel FPGA devices. The methods to boot up Nios® V processor vary according to the flash memory selection and device families.

Table 23.  Supported Flash Memories with Respective Boot Options
Supported Boot Memories Device Nios® V Processor Booting Methods Application Runtime Location Boot Copier
Configuration QSPI Flash (for Active Serial configuration) Control block-based devices (with Generic Serial Flash Interface Intel FPGA IP) 2

Nios® V processor application execute-in-place from configuration QSPI flash

Configuration QSPI flash (XIP) + OCRAM/ External RAM (for writable data sections) alt_load() function
Nios® V processor application copied from configuration QSPI flash to RAM using boot copier OCRAM/ External RAM GSFI bootloader
SDM-based devices (with Mailbox Client Intel FPGA IP). 2 Nios® V processor application copied from configuration QSPI flash to RAM using boot copier OCRAM/ External RAM SDM bootloader

On-chip Memory (OCRAM)

All supported Intel® FPGA devices 2 Nios® V processor application execute-in-place from OCRAM OCRAM alt_load() function
Tightly Coupled Memory (TCM) All supported Intel® FPGA devices2 Nios® V processor application execute-in-place from TCM Instruction TCM (XIP) + Data TCM (for writable data sections) None
Figure 16.  Nios® V Processor Boot Flow
2 Refer to AN 980: Nios® V Processor Intel® Quartus® Prime Software Support for the device list.