Nios® V Embedded Processor Design Handbook

ID 726952
Date 12/04/2023
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4.4.2.1. GSFI Bootloader

The GSFI bootloader is the Nios® V processor boot copier that supports QSPI flash memory in control block-based devices. The GSFI bootloader includes the following features:
  • Locates the software application in non-volatile memory.
  • Unpacks and copies the software application image to RAM.
  • Automatically switches processor execution to application code in RAM after copy completes.
The boot image is located right after the boot copier. You need to ensure the Nios® V processor reset offset points to the start of the boot copier. The Figure: Memory Map for QSPI Flash with GSFI Bootloader memory map for QSPI Flash with GSFI Bootloader shows the flash memory map for QSPI flash when using a boot copier. This memory map assumes the flash memory memory stores the FPGA image and the application software.
Table 25.  GSFI Bootloader for Nios® V Processor Core
Nios® V Processor Core GSFI Bootloader File Location
Nios® V/m processor <Intel Quartus Installation Directory>/niosv/components/bootloader/niosv_m_bootloader.srec
Nios® V/g processor <Intel Quartus Installation Directory>/niosv/components/bootloader/niosv_g_bootloader.srec
Figure 17. Memory Map for QSPI Flash with GSFI Bootloader
Note:
  1. At the start of the memory map is the FPGA image followed by your data, which consists of boot copier and application code.
  2. You must set the Nios® V processor reset offset in Platform Designer and point it to the start of the boot copier.
  3. The size of the FPGA image is unknown.You can only know the exact size after the Intel® Quartus® Prime project compilation. You must determine an upper bound for the size of the Intel FPGA image. For example, if the size of the FPGA image is estimated to be less than 0x01E00000, set the Reset Offset to 0x01E00000 in Platform Designer, which is also the start of the boot copier.
  4. A good design practice consists of setting the reset vector offset at a flash sector boundary to ensure no partial erase of the FPGA image occurs in case the software application is updated.