Nios® V Embedded Processor Design Handbook

ID 726952
Date 12/04/2023
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4.7.1.1. Hardware Design Flow

The following sections describe a step-by-step method for building a bootable system for a Nios® V processor application from TCM. The example below is built using Intel Arria 10 SoC development kit.

IP Component Settings

  1. Create your Nios® V processor project using Intel® Quartus® Prime and Platform Designer.
    Figure 83. Connections for Nios® V Processor Project

TCM Settings for Nios® V Processor

  1. In the Nios® V processor parameter editor, enable the Instruction TCM1 and Data TCM1.
  2. Initialize Instruction TCM1 with itcm.hex.
  3. Initialize Data TCM1 with dtcm.hex.
Figure 84. Instruction TCM1 Settings
Figure 85. Data TCM1 Settings

Reset Agent Settings for Nios® V Processor

  1. In the Nios® V processor parameter editor, set the Reset Agent to Instruction TCM1.
    Figure 86. Reset Agent Settings for Nios® V Processor
  2. Click Generate HDL, the Generation dialog box appears.
  3. Specify output file generation options and then click Generate.

Intel® Quartus® Prime Settings

  1. In the Intel Quartus Prime software, click Assignment > Device > Device and Pin Options > Configuration.
  2. Set Configuration scheme according to your FPGA configuration scheme
  3. Click OK to exit the Device and Pin Options window.
  4. Click OK to exit the Device window.
  5. Click Start Compilation to compile your project.