Nios® V Embedded Processor Design Handbook

ID 726952
Date 12/04/2023
Public
Document Table of Contents
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2.1.1. Instantiating Nios® V Processor Intel® FPGA IP

You can instantiate any of the processor IP cores in Platform Designer > IP Catalog > Processors and Peripherals > Embedded Processors.
The IP core of each processor supports different configuration options based on its unique architecture. You can define these configurations to better suit your design needs.
Table 3.  Configuration Options Across Core Variants
Configuration Options Nios® V/c Processor Nios® V/m Processor Nios® V/g Processor
Debug
Use Reset Request
Vectors
CPU Architecture
ECC
Caches, Peripheral Regions and TCMs
Custom Instructions