Nios® V Embedded Processor Design Handbook

ID 726952
Date 12/04/2023
Public
Document Table of Contents

2.1.1.2.4. CPU Architecture

Table 10.  CPU Architecture Tab Parameters
CPU Architecture Description
Enable Pipelining in CPU
  • Enable this option to instantiate pipelined Nios® V/m processor.
    • IPC is higher at the cost of higher logic area and lower Fmax frequency.
  • Disable this option to instantiate non-pipelined Nios® V/m processor.
    • Has similar core performance with the Nios® V/c processor.
    • Supports debugging and interrupt capability
    • Lower logic area and higher Fmax frequency at the cost of lower IPC.