Nios® V Embedded Processor Design Handbook

ID 726952
Date 12/04/2023
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5.4.4. Hardware Design Files

Despite the example designs functioned differently, they share similar hardware design and BSP settings. The only difference lies in their respective Nios V application source code, one for the Simple Socket Server application, while the other for the iPerf 2 application.

The µC/TCP-IP example designs are developed using the Platform Designer. The hardware files can be generated using the build_sof.py Python script. The example design consist of:

  • Nios® V Processor Intel FPGA IP
  • On-Chip Memory II Intel FPGA IP for System Memory and Descriptor Memory
  • JTAG UART Intel FPGA IP
  • System ID Peripheral Intel FPGA IP
  • Parallel I/O Intel FPGA IP (PIO)
  • Modular Scatter-Gather DMA Intel FPGA IP (mSGDMA)
  • Triple-Speed Ethernet Intel FPGA IP (TSE)
Figure 93. Hardware Block Diagram
Note:
  • (1) The first n bytes are reserved for mSGDMA descriptor buffers, where n is the number of bytes taken by the configured RX or TX buffers. Applications must not use this memory region.
  • (2) For MAC variations without internet FIFO buffers, the transmit and receive FIFOs are external to the MAC function.
  • (3) Only one buffer type (RX or TX buffers) can reside in the descriptor memory.