Nios® V Embedded Processor Design Handbook

ID 726952
Date 12/04/2023
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2.1.1.3.4. Memory Configurations Tab

Table 15.  Memory Configuration Tab Parameters
Category Memory Configuration Tab Description
Caches Data Cache Size
  • Specifies the size of the data cache.
  • Valid sizes are from 1 kilobytes (KB) to 16 KB.
Instruction Cache Size
  • Specifies the size of the instruction cache.
  • Valid sizes are from 1 KB to 16 KB.
Peripheral Region A and B Size
  • Specifies the size of the peripheral region.
  • Valid sizes are from 64 KB to 2 gigabytes (GB), or None. Choosing None disables the peripheral region.
Base Address
  • Specifies the base address of peripheral region after you select the size.
  • All addresses in the peripheral region produce uncacheable data accesses.
  • Peripheral region base address must be aligned to the peripheral region size.
Tightly Coupled Memories Size
  • Specifies the size of the tightly-coupled memory.
    • Valid sizes are from 0 MB to 512 MB.
Base Address
  • Specifies the base address of tightly-coupled memory.
Initialization File
  • Specifies the initialization file for tightly-coupled memory.
Note: In a Nios® V processor system with cache enabled, you must place system peripherals within a peripheral region. You can use peripheral regions to define a non-cacheable transaction for peripherals such as UART, PIO, DMA, and others.