Nios® V Embedded Processor Design Handbook

ID 726952
Date 12/04/2023
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4.5.1.2.1. Hardware Design Flow

The following sections describe a step-by-step method for building a bootable system for a Nios V processor application copied from configuration QSPI flash to RAM using GSFI Bootloader. The following example is built using Intel Arria 10 SoC Development Kit.

IP Component Settings

  1. Create your Nios® V processor project using Intel® Quartus® Prime and Platform Designer.
  2. Add the Generic Serial Flash Interface Intel FPGA IP is into your Platform Designer system.
    Figure 36. Connections for Nios V Processor Project
    Figure 37. Generic Serial Flash Interface Intel FPGA IP Parameter Settings
  3. Change the Device Density (Mb) according to the QSPI flash size.
  4. Change the addressing mode by modifying bit 8 of the Control Register value in the Default Settings parameter section. Changing bit 8 to 0x0 enables 3-byte addressing, or 0x1 enables 4-byte addressing
Note: Refer to Intel Supported Configuration Devices tab > Intel Supported Third Party Configuration Devices in Device Configuration Support Center to check the byte addressing mode supported for each flash device in each Intel FPGA device.

For example, Intel® Arria® 10 devices when used with Micron flash devices support the 4-byte addressing mode.

Reset Agent Settings for Nios® V Processor Boot-copier Method

  1. In the Nios® V processor parameter editor, set the Reset Agent to QSPI Flash.
    Note: Your SOF image size influences your reset offset configuration. The reset offset is the start of the address of the HEX file in QSPI flash and it must point to a location after the SOF image. If the SOF image space and the reset offset location overlap, Intel® Quartus® Prime software displays and overlap error. You can determine the minimum reset offset by using the configuration bitstream size from the device datasheet.

    For example, the uncompressed configuration bitstream size for Intel® Arria® 10 GX 660 is 252,959,072 bits (31,619,884 bytes). If the SOF image starts at address 0x0, the SOF image can extend up to address 0x1E27FFF (0x1E27B2C). In this case, the minimum reset offset you can select is 0x2000000.

    Figure 38. Nios V Parameter Editor Settings
  2. Click Generate HDL, the Generation dialog box appears.
  3. Specify output file generation options and then click Generate.

Intel® Quartus® Prime Software Settings

  1. In the Intel Quartus Prime software, click Assignment > Device > Device and Pin Options > Configuration .
  2. Set Configuration scheme to Active Serial x4 (can use Configuration Device).
  3. Set the Active serial clock source to 100 MHz Internal Oscillator.
    Figure 39. Device and Pin Options
  4. Click OK to exit the Device and Pin Options window.
  5. Click OK to exit the Device window.
  6. Click Start Compilation to compile your project.