Nios® V Embedded Processor Design Handbook

ID 726952
Date 12/04/2023
Document Table of Contents
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2.2.2. Connecting Signals and Assigning Physical Pin Locations

To connect your Intel FPGA design to your board-level design, perform the following tasks:

  • Identify the top-level file for your design and signals to connect to external Intel FPGA device pins.
  • Understand which pins to connect through your board-level design user guide or schematics.
  • Assign signals in the top-level design to pin your Intel FPGA device with pin assignment tools.

The top-level Intel® FPGA IP-based design can be your Platform Designer system. However, the Intel FPGA can also include additional design logic based on your needs and thus introduces a custom top-level file. The top-level file connects the Nios® V processor system module signals to other Intel FPGA design logic.