Nios® V Embedded Processor Design Handbook

ID 726952
Date 12/04/2023
Public
Document Table of Contents

8.3.7. Operating the Example Design

To display the application messages, the example design utilizes the JTAG UART Intel® FPGA IP. You can begin the display message by using the following command:

juart-terminal
Figure 135. Output Result from CRC Decoders