Nios® V Embedded Processor Design Handbook

ID 726952
Date 12/04/2023
Public
Document Table of Contents
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2.1.1.2.1. Debug Tab

Table 7.  Debug Tab Parameters
Debug Tab Description
Enable Debug
  • Enable this option to add the JTAG target connection module to the Nios® V processor.
  • The JTAG target connection module allows connecting to the Nios® V processor through the JTAG interface pins of the FPGA.
  • The connection provides the following basic capabilities:
    • Start and stop the Nios® V processor
    • Examine and edit registers and memory.
    • Download the Nios® V application .elf file to the processor memory at runtime via niosv-download.
    • Debug the application running on the Nios® V processor
  • Connect dm_agent port to the processor instruction and data bus. Ensure the base address between both buses are the same.
Enable Reset from Debug Module
  • Enable this option to expose dbg_reset_out and ndm_reset_in ports.
  • JTAG debugger or niosv-download -r command trigger the dbg_reset_out, which allows the Nios® V processor to reset system peripherals connecting to this port.
  • You must connect the dbg_reset_out interface to ndm_reset_in instead of reset interface to trigger reset to processor core and timer module.