Nios® V Embedded Processor Design Handbook

ID 726952
Date 12/04/2023
Public
Document Table of Contents
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6.1. Debugging Nios® V/c Processor

Nios® V/c processor implements the compact architecture to achieve a smaller logic size by applying the following trait:
  • Non-pipelined datapath
  • No debug module
  • No processor CSR
  • No interrupts and exceptions
  • No internal timer module

The Nios® V/c processor core is limited to hardware debugging without the debug module. Software debugging is not applicable for the Nios® V/c processor core.

Intel recommends to use the non-pipelined Nios® V/m processor to allow full debugging capabilities. The architecture performance of a non-pipelined Nios® V/m processor is similar to the Nios® V/c processor, at the expense of bigger logic size.

Table 39.   Nios® V/c and Nios® V/m Processor Core
Feature Nios® V/c Processor Non-pipelined Nios® V/m Processor
Debug Module Supported
Processor CSR Supported
Interrupt and Exceptions Supported
Logic Size (ALM) 10 x1 x1.5
DMIPS/Mhz Performance10 x1 x1
CoreMark/MHz Performance10 x1 x1
Internal Timer Supported
10 Relative to the Nios® V/c processor.