Nios® V Embedded Processor Design Handbook

ID 726952
Date 12/04/2023
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8.2.7. Operating the Example Design

To display the application messages, the example design utilizes the JTAG UART Intel FPGA IP. You can begin the display message by using the following command:

juart-terminal
Figure 132. Output Result from PE1
Figure 133. Output Result from PE2