Nios® V Embedded Processor Design Handbook

ID 726952
Date 12/04/2023
Public
Document Table of Contents

7.3.2.1. Create a Platform Designer System

  1. Add the Nios® V processor and the following peripherals into the Platform Designer system:
    • Nios® V/m Processor Intel® FPGA IP
    • On-Chip Memory (RAM) Intel® FPGA IP
    • JTAG UART Intel® FPGA IP
    • Mailbox Client Intel® FPGA IP
    • JTAG to Avalon Master Bridge Intel® FPGA IP
    Figure 113. Connections in Platform Designer System
  2. In the Nios® V processor Parameters tab
    • Enable the Enable Debug feature.
    • Set the Reset Agent to OCRAM.
    Figure 114.  Nios® V Processor Intel® FPGA IP Parameter Editor
  3. In the On-Chip Memory (RAM or ROM) Intel FPGA Parameters tab Total memory size box, specify the memory size as below:
    • 1 Mbytes for application system
    • 6 Mbytes for factory system.
  4. Enable Initialize memory content and Enable non-default initialization file with app.hex in the OCRAM.
    Figure 115. On-Chip Memory Intel FPGA IP Parameter Editor
  5. Click Generate HDL, the Generation dialog box appears.
  6. Specify output file generation options and then click Generate.