Nios® V Embedded Processor Design Handbook

ID 726952
Date 12/04/2023
Public
Document Table of Contents

8.3.4. Hardware Design Files

The CRC Custom Instruction Design on Nios® V/g processor is developed using the Platform Designer. You can generate the hardware files using the build_sof.py Python script.

The example design consists of:

  • Nios® V Processor Intel® FPGA IP
  • On-Chip Memory II Intel® FPGA IP
  • JTAG UART Intel® FPGA IP
  • CRC Processing Engine
Figure 134. Example Design Block Diagram