Nios® V Embedded Processor Design Handbook

ID 726952
Date 12/04/2023
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4.7.1. Nios® V Processor Application Executes in-place from TCM

The tightly coupled memories are initialized during FPGA configuration with data from a Nios® V processor application image. This data is built into the FPGA configuration bitstream. This process eliminates the need for a boot copier, as the Nios® V processor application is already in place at system reset.

Figure 81.  Nios® V Processor Application Executes In-Place from OCRAM when FPGA Device Configured from QSPI Flash
Figure 82. Design, Configuration, and Booting Flow