Nios® V Embedded Processor Design Handbook

ID 726952
Date 12/04/2023

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Document Table of Contents

2.3.3. On-Chip Memory Configuration – RAM or ROM

You can configure Intel FPGA On-Chip Memory IPs as RAM or ROM.
  • RAM provides read and write capability and has a volatile nature. If you are booting the Nios® V processor from an On-Chip RAM, you must make sure boot content is preserved and not corrupted in the event of a reset during run time.
  • If a Nios® V processor is booting from ROM, any software bug on the Nios® V processor cannot erroneously overwrite the contents of On-Chip Memory. Thus, reducing the risk of boot software corruption.