Nios® V Embedded Processor Design Handbook

ID 726952
Date 12/04/2023
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10. Document Revision History for the Nios® V Embedded Processor Design Handbook

Document Version Intel® Quartus® Prime Version Changes
2023.12.04 23.4
  • Updated the note to refer to AN 980: Nios V Processor Intel Quartus Prime Software Support throughout the document.
  • Updated the titles and figures in Instantiating Nios V Processor Intel FPGA IP for the following Nios® V processor cores:
    • Nios® V/c Compact Microcontroller Processor Intel® FPGA IP
    • Nios® V/m Microcontroller Intel® FPGA IP
    • Nios® V/g General Purpose Processor Intel® FPGA IP
  • Updated the table: CPU Architecture to remove atomic extensions.
  • Added the command for Intel® Quartus® Prime Standard Edition version in the following topics:
    • Table: GUI Tools and Command-line Tools Tasks Summary.
    • Topic: Generating the Board Support Package in Creating Nios V Processor Software.
  • Edited the title for Example Design on Unimplemented Instruction (Custom Instruction Design on Nios® V/g processor) to Unimplemented Instruction Example Design.
  • Added topic Hardware Acceleration Example Designs.
2023.10.02 23.3
  • Added new topics based on new addition Nios® V/c processor:
    • Nios® V Processor Licensing
    • Instantiating Nios® V Processor IP Core
    • Instantiating Nios® V/c Processor Intel® FPGA IP
    • Instantiating Nios® V/m Processor Intel® FPGA IP
    • Instantiating Nios® V/g Processor Intel® FPGA IP
    • Debugging Nios® V/c Processor
    • Steps to Debug Nios® V/c Processor
  • Updated Nios® V Processor Configuration and Booting Solutions with TCM related in the following topics:
    • Nios® V Processor Booting Methods
    • Added Nios® V Processor Application Execute-In-Place from TCM
    • Added Nios® V Processor Booting from Tightly Coupled Memory (TCM)
    • Summary of Nios® V Processor Vector Configuration and BSP Settings
  • Updated the mention of Nios® V/m to Nios® V in related topics with the release of Nios® V/g and Nios® V/c processors.
2023.09.01 23.2
  • Updated Software Design Flow in Processor Application Executes-In-Place from Configuration QSPI Flash:
    • Updated figures:
      • Linker Region Settings When Exceptions is set to OCRAM / External RAM.
      • Linker Region Settings When Exceptions is set to QSPI Flash .
    • Added steps to disable gsfi driver.
  • Added new section: Nios® V Processor RSU Quick Start Guide in SDM-based Devices.
  • Updated figure Nios® V Processor System Design Flow in the topic Embedded System Design.
2023.05.26 23.1
  • Added links to AN 980: Nios® V Processor Intel® Quartus® Prime Software Support.
  • Added a new section: Nios® V Processor — Using Custom Instruction.
2023.04.10 23.1
  • Added new topics:
    • Caches and Peripheral Regions Tab
    • Custom Instruction Tab
  • Added table GSFI Bootloader for Nios V Processor Core in the topic GSFI Bootloader.
  • Added a new step in the topic Generating HEX File from the section Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (GSFI Bootloader).
  • Updated product family name to " Intel Agilex® 7".
Document Version Intel® Quartus® Prime Version IP Version Changes
2023.02.14 22.4 22.4.0
  • Edited topic Intel® Quartus® Prime Software Support.
  • Edited topic Nios V/m Processor Example Design.
  • Added a note in the following topics to refer to the topic Intel® Quartus® Prime Software Support
    • Generating the Board Support Package using the BSP Editor GUI
    • Nios V Board Support Package Editor
    • Software Design Flow
    • Creating a BSP project
  • Updated the following topics to align with the design store migration steps:
    • Generating the Application Project File
    • GSFI Bootloader Example Design
    • SDM Bootloader Example Design
    • MicroC/TCP-IP Example Designs: Overview
    • Acquiring the Example Design Files
    • Creating an Application Project
    • Device Programming
    • Optional Configuration
  • Removed the following topics:
    • Generating the Example Design Through Graphical User Interface
    • Generating the Nios V/m Processor Example Design Using the Command Line Interface
    • Generate Nios V processor example design from Platform Designer
    • HEX File Generation
2022.10.31 22.1std 1.0.0
  • Updated references from Intel® Quartus® Prime Pro Edition to Intel® Quartus® Prime to indicate support for both Pro and Standard Edition.
  • Added new topic: Intel® Quartus® Prime Software Support.
2022.10.25 22.3 22.3.0
  • Added new section: Nios V Processor — Remote System Update.
2022.09.26 22.3 22.3.0
  • Updated Configure Nios V Processor Parameters
    • Edited Debug Tab
    • Added Use Reset Request Tab
    • Edited Vectors Tab. Removed Exception Agent and Exception Offset
  • Updated the following figures:
    • Nios V/m Processor IP instance in Platform Designer
    • Example connection of Nios V processor with other peripherals in Platform Designer
    • hal.linker Settings for QSPI Flash
    • Connections for Nios V Processor Project
    • hal.linker Settings
    • Linker Region Settings
    • hal.make Settings
    • BSP Driver tab
  • Added Enable Reset from Debug Module to the following figures:
    • Parameter Editor Settings
    • Nios V Parameter Editor Settings
  • Removed the mention of exception vector, exception RAM, exception agent, and .exception in the following topics:
    • Defining System Component Design
    • Nios V Processor Design, Configuration and Boot Flow (Control Block-based Device)
    • Reset Agent Settings for Nios V Processor Execute-In-Place Method
    • Reset Agent Settings for Nios V Processor Boot-copier Method
    • Nios V Processor Design, Configuration and Boot Flow (SDM-based Devices)
    • Nios V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (SDM Bootloader)
    • Table: Description of Memory Organization
    • Design, Configuration and Booting Flow in Nios V Processor Application Executes in-place from OCRAM
    • Table: Summary of Nios V Processor Vector Configurations and BSP Settings
  • Edited Configuring BSP Editor and Generating the BSP Project in Nios V Processor Design, Configuration and Boot Flow (Control Block-based Device).
  • Added Table: Settings for BSP Editor in Software Design Flow (SDM Bootloader Project).
2022.08.12 22.2 21.3.0
  • Edited the steps in Programming Nios V/m into the FPGA Device.
  • Edited Table: Debug Tab Parameter to add the description for dbg_reset.
  • Edited topic On-Chip Memory Configuration - RAM or ROM topic. Added a link to Nios V Processor Application Execute-In-Place from OCRAM.
  • Changed the topic title from Clocks and Resets to Clocks and Resets Best Practices.
  • Added the following new topics:
    • Reset Request Interface
    • Typical Use Cases
    • Assigning a Default Agent
  • Added a note about configuring the RISC-V toolchain prefix in the topic Eclipse CDT for Embedded C/C++ Developer.
2022.06.21 22.2 21.3.0
  • Added the support for RiscFree IDE for Intel® FPGAs.
  • Removed the following topics:
    • Setting Up Open-Source Tools
    • Building the Application Project using Eclipse Embedded CDT
    • Building the Application Project using the Command-Line Interface
    • Creating a Software Project using Platform Designer & Eclipse Embedded CDT
    • Creating a Software Project Using Command Line
  • Edited the Figure : Software Design Flow to include RiscFree IDE for Intel® FPGAs
  • Added the following topics:
    • Nios V Software Development Flow
    • Board Support Package Project
    • Application Project
    • Intel FPGA Embedded Development Tools
    • Nios V Board Support Package Editor
    • RiscFree* IDE for Intel FPGA
    • Eclipse* CDT for Embedded C/C++ Developer
    • Nios V Utilities Tools
    • File Format Conversion Tools
    • Other Utilities Tools
    • Generating the Board Support Package
    • Generating the Application Project File
    • Building the Application Project
2022.04.04 22.1 21.2.0 Initial release.