Nios® V Embedded Processor Design Handbook

ID 726952
Date 12/04/2023
Public
Document Table of Contents
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7.3.5.2. Programming the Update Images

  1. Ensure that the Intel FPGA device’s Active Serial (AS) pin is routed to the QSPI flash. This routing allows the flash loader to load into the QSPI flash and configure the board correctly.
  2. Ensure the MSEL pin setting on the board is configured for AS programming.
  3. Open the Intel Quartus Prime Configuration Debugger and make sure JTAG is detected under the Hardware Setup.
  4. Click Load Device and select the Intel FPGA device.
  5. Navigate to the Flash tab.
  6. Click Auto-detect to auto-detect the QSPI Flash that is attached to the device.
  7. Navigate to the Program function. Assign Image Start Address and RPD file path.
    • For app_image.rpd, the Image Start Address is 0x3000000.

    • For factory_update.rpd, the Image Start Address is 0x3800000.

  8. Click Program RPD to begin.
    Figure 129. Configuration Debugger - Flash
    Figure 130. Quad SPI Flash Address Map

Memory Map File of Initial RSU JIC Image

BLOCK                         START ADDRESS   END ADDRESS     

BOOT_INFO                     0x00000000      0x0010FFFF
FACTORY_IMAGE                 0x00110000      0x0084FFFF (0x0080CFFF)
SPT0                          0x00850000      0x00857FFF
SPT1                          0x00858000      0x0085FFFF
CPB0                          0x00860000      0x00867FFF
CPB1                          0x00868000      0x0086FFFF
App-0                         0x01000000      0x01432FFF


Configuration device: 1SX280LU2
Configuration mode: Active Serial x4